High density semiconductor fabrication techniques are required for the manufacture of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) chips having up to several million devices thereon. High density chips may be fabricated by shrinking the size of the individual devices on the chips so that more devices per unit area may be formed. When device sizes shrink, however, it becomes more difficult to provide interconnection between devices. If small size devices cannot be connected to one another as required, the benefits of small device size are lost.
The art has provided many techniques for forming dense metal interconnection patterns for device interconnection. High density VLSI and ULSI devices typically require multiple levels of surface metallization in order to accommodate their complex wiring patterns. Unfortunately, multiple level metallization creates planarity problems in the metallization layers, thereby limiting interconnection density. Complex process steps are also needed to provide multiple levels of metallization.
Another concern in shrinking device size is the difficulty of providing adequate isolation between devices. Semiconductor On Insulator (SOI) technology may be employed to enhance isolation between devices. One method for fabricating an SOI structure oxidizes first and second silicon substrates to form a layer of silicon dioxide (SiO.sub.2) on each. The silicon dioxide surfaces ar bonded together face-to-face to form a unified structure. Most of the silicon may be etched from one of the wafers until only several micrometers of silicon remain. Devices are then formed in this thin film of silicon. Another version of this type of silicon oxide bonding technique is disclosed in an article by Laskey entitled "Wafer Bonding for Silicon-On-Insulator Technologies," Applied Physics Letters, Vol. 48, No. 1, Jan. 6, 1986. Other examples of silicon oxide bonding techniques are disclosed in U.S. Pat. No. 3,997,381 to Wanlass, and in U.S. Pat. No. 4,601,779 to Abernathy et al.